In the effort to obtain the fastest possible computational throughput, digital computer architecture generally employs either parallel or pipeline processing techniques and the fastest-available cost-effective hardware. Parallel processing divides the data to be processed among concurrently operating arithmetic and logical units thereby obtaining faster processing by a factor that depends upon the number of individual, concurrently operating, arithmetic and logical units utilized. Pipeline processing divides the function to be evaluated into separable operations that are implemented in serially connected and latched pipeline stages. The data to be processed is streamed through the pipeline thereby obtaining faster processing by a factor that depends upon the number of pipeline stages utilized. Vector processors are commonly employed for the important class of problems calling for the repetitive evaluation of a computationally intensive function on blocks of data arrayed into sets or vectors. In such machines, the pipeline is typically configurable in one of a plurality of architectures each corresponding to a preselected function to be evaluated on sequentially applied data vectors. In the known vector processors, vector data I/O, vector data address generation, and pipeline control are interdependently performed which presents a material impediment to system throughput. In addition, system throughput is limited by the dependence of memory cycle timing on the absolute values of the addresses, and by the failure of the pipeline architectures to attain 100 percent utilization of the pipeline arithmetical units for each one of a plurality of functions to be evaluated, among other things.